Semiconductor package including a molding layer
AssigneeSamsung Electronics Co., Ltd.
InventorHAE-JUNG YU
Life of this patent
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Abstract
A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.
Claims20
A method for fabricating a semiconductor package, comprising:
- forming a first molding layer covering sidewalls of the substrate;
- providing a first semiconductor chip on a first surface of the substrate and a second surface of the first molding layer;
- and
- forming a second molding layer directly on the substrate and the first molding layer, covering sidewalls of the first semiconductor chip,
- wherein the first semiconductor chip includes a first region and a second region,
- wherein the first region vertically overlaps with the substrate, and
- wherein the second region vertically overlaps with the first molding layer.
A method for fabricating a semiconductor package, comprising:
- providing an interposer substrate on a carrier substrate;
- forming a first molding layer on the carrier substrate, covering the sidewalls of the interposer substrate;
- mounting a first semiconductor chip on the interposer substrates;
- forming a second molding layer on the first molding layer and the interposer substrate, covering the sidewalls of the first semiconductor chip;
- removing the carrier substrate to expose the bottom surface of the interposer substrate and the bottom surface of the first molding layer;
- and
- performing a thinning process on the interposer substrate and the first molding layer together.
A method for fabricating a semiconductor package, comprising:
- forming a first molding layer covering sidewalls of the interposer substrate;
- mounting a first semiconductor chip and a second semiconductor chip, horizontally spaced apart from the first semiconductor chip, on the interposer substrate, wherein the first semiconductor chip has a mounting region that vertically overlaps with the interposer substrate and an overhang region that vertically overlaps with the first molding layer;
- forming first bumps between the interposer substrate and the first semiconductor chip;
- forming second bumps between the interposer substrate and the second semiconductor chip;
- and
- forming an underfill layer between the interposer substrate and the first lower semiconductor chip, and between the interposer substrate and the second semiconductor chip, encapsulating the first and second bumps,
- wherein the underfill layer extends between a top surface of the first molding layer and a bottom surface of the overhang region of the first lower semiconductor chip.
Dependencies are inferred from the claim text.