US 2024/0404973 A1Published application

Wafer level process for semiconductor device package

OwnerMohamad Ashraf bin Mohd Arshad, Jeffrey Salvacion Solas +4inventors

InventorsMohamad Ashraf bin Mohd Arshad, Jeffrey Salvacion Solas, Ruby Ann Merto Camenforte, Huay Yann Tay, Chia Wei Chang, Xiaolei Liao

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Abstract

An example semiconductor device package includes a semiconductor die having bond pads on a device side surface, and a build-up routing layer on the semiconductor die including: connection level conductors directly contacting the bond pads; trace level conductors on the connection level conductors directly contacting distal ends of the connection level conductors; dielectric material surrounding the connection level conductors and the trace level conductors; terminals formed of portions of a top layer of the trace level conductors having a board side surface exposed from the dielectric material, wherein an electrical connection between the terminals and the bond pads is formed without a solder joint or a bond wire; and mold compound covering a portion of the semiconductor die, the trace level conductors and the connection level conductors of the build-up routing layer, wherein the board side surface of the terminals is exposed from the mold compound.

Claims24

Dependent claims

A method, comprising:

forming semiconductor dies on a semiconductor wafer, the semiconductor dies having bond pads on a device side surface and having an opposing backside surface;
forming a build-up routing layer over the semiconductor wafer by performing:
patterning connection level conductors over the device side surface of the semiconductor dies to form post connects directly contacting the bond pads of the semiconductor dies and extending to a distal end;
forming a first layer of dielectric material over and surrounding the post connects;
grinding the first layer of dielectric material to expose the distal ends of the post connects;
patterning trace level conductors on the first layer of dielectric material, the trace level conductors directly contacting distal ends of the post connects;
depositing a second layer of dielectric material over the connection level conductors and the trace level conductors;
and
grinding the second dielectric layer to expose a surface of the trace level conductors, portions of the exposed surface of a top layer of the trace level conductors forming terminals for semiconductor device packages;
cutting through the build-up routing layer in scribe lanes between the semiconductor dies to form trenches extending into the semiconductor wafer;
backgrinding the semiconductor wafer on the backside surface of the semiconductor wafer to form openings by exposing the trenches to separate the semiconductor dies from one another;
and
covering a portion of the device side surface of the semiconductor dies, a portion of the build-up routing layer, and the openings between the semiconductor dies with mold compound, while the terminals formed of the trace level conductors are exposed from the mold compound.

10 more elements

Dependencies are inferred from the claim text.