Flip-chip semiconductor-on-insulator transistor layout
AssigneeSkyworks Solutions, Inc.
InventorsYang Liu, Yong Hee Lee, Thomas Obkircher
Life of this patent
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Abstract
A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.
Claims21
(canceled)
A semiconductor-on-insulator die comprising:
- a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer;
- at least one contact pad, the second metal layer between the at least one contact pad and the first metal layer;
- a transistor including a first terminal, the first terminal formed within the active layer;
- and
- a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad.
A packaged module comprising:
- a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer, the die further including at least one contact pad and a transistor including a first terminal, the first terminal formed within the active layer, the second metal layer between the at least one contact pad and the first metal layer;
- a ground plane electrically connected to the at least one contact pad;
- and
- a conductive path extending between the first terminal and the ground plane through at least the first metal layer, the second metal layer, and the at least one contact pad, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the ground plane.
A power amplifier system comprising:
- a semiconductor-on-insulator die including a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a second metal layer, the first metal layer between the active layer and the second metal layer, the die further including at least one contact pad and a transistor including a first terminal, the first terminal formed within the active layer, the second metal layer between the at least one contact pad and the first metal layer;
- and
- a power amplifier configured to amplify a radio frequency signal and including a first transistor formed in the semiconductor-on-insulator die, the first transistor including a first terminal formed within the active layer of the semiconductor-on-insulator die, a conductive path extending between the first terminal and the at least one contact pad through at least the first metal layer and the second metal layer, at least a first portion of the conductive path extending in a straight-line path from the first terminal to the at least one contact pad.
Dependencies are inferred from the claim text.