Metal interconnect layers for fet architectures
AssigneeInternational Business Machines Corporation
InventorsSON NGUYEN, Ruilong Xie, Kisik Choi, Hosadurga Shobha
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Abstract
Low-k, carbon-rich silicon carbonitride or silicon oxycarbonitride interlevel dielectric layers having good copper and oxidation barrier properties are employed to facilitate the manufacture and reliability of integrated circuits, including structures including back side power rails. Such interlevel dielectric layers enable copper to copper or copper to metal bonding without copper or metal diffusion into dielectric material, even with some misalignment.
Claims20
A multi-layer semiconductor structure, comprising:
- a device layer comprising field-effect transistors and including a front side and a back side;
- a first interconnect layer above the front side of the device layer and electrically connected to the device layer;
- a back side power distribution network below the back side of the device layer, the back side power distribution network including a top metal interconnect layer, a bottom metal interconnect layer, and bottom vias electrically connecting the top metal interconnect layer and the bottom metal interconnect layer;
- a silicon substrate between the back side power distribution network and the device layer;
- through silicon vias extending vertically within the silicon substrate, the through silicon vias being electrically connected to the device layer and having bottom ends adjoining the top metal interconnect layer of the back side power distribution network;
- a silicon carbonitride and/or silicon oxycarbonitride low-k interlevel dielectric layer beneath the silicon substrate, the interlevel dielectric layer having a composition of greater than fifty atomic percent carbon, less than ten atomic percent nitrogen, and less than ten atomic percent oxygen, the low-k interlevel dielectric layer having a top surface adjoining the silicon substrate, the top metal interconnect layer and the bottom vias being embedded within the low-k interlevel dielectric layer.
A multi-layer semiconductor structure, comprising:
- a device layer including a front side and a back side, the device layer comprising:
- field-effect transistors within a front side interlevel dielectric layer, each of the field-effect transistors including a channel region, a gate stack adjoining the channel region, and first and second source/drain regions extending laterally from the channel region;
- a back-end-of-line interconnect layer over the front side of the device layer, the back-end-of-line interconnect layer being electrically connected to the device layer;
- a back side power distribution network;
- a silicon carbonitride and/or silicon oxycarbonitride low-k back side interlevel dielectric layer between the device layer and the back side power distribution network, the low-k back side interlevel dielectric layer having a composition of greater than fifty atomic percent carbon, less than ten atomic percent nitrogen, and less than ten atomic percent oxygen;
- and
- electrically conductive interconnects embedded within the low-k back side interlevel dielectric layer, the device layer and the back side power distribution network being electrically connected by the electrically conductive interconnects.
A method of fabricating a multi-layer semiconductor structure, comprising:
- forming a device layer including field-effect transistors;
- forming one or more front side metal interconnect layers over a front side of the device layer;
- and
- forming a back side interconnect layer over a back side of the device layer, the back side interconnect layer including a low-k interlevel dielectric layer and metal conductors embedded within the low-k interlevel dielectric layer, the low-k interlevel dielectric layer comprising silicon carbonitride and/or silicon oxycarbonitride having a composition of greater than fifty atomic percent carbon, less than ten atomic percent nitrogen, and less than ten atomic percent oxygen.
Dependencies are inferred from the claim text.