Semiconductor device including data storage structures

A semiconductor device, comprising:

• a plurality of word lines stacked and spaced apart from each other in a first direction, wherein each word line of the plurality of word lines extends in a second direction perpendicular to the first direction;
• a plurality of active layers stacked and spaced apart from each other in the first direction, wherein each active layer of the plurality of active layers comprises a channel region vertically overlapping the word lines;
• a bit line extending in the first direction and connected to first sides of the plurality of active layers;
• and
• a plurality of data storage structures stacked and spaced apart from each other in the first direction and connected to second sides of the plurality of active layers, wherein the plurality of active layers are disposed between the bit line and the data storage structures,
• wherein each data storage structure of the plurality of data storage structures comprises a first electrode, a second electrode spaced apart from the first electrode, and a dielectric layer between the first electrode and the second electrode,
• wherein the first electrodes of the plurality of data storage structures are connected to the second sides of the plurality of active layers, and
• wherein the second electrodes of the plurality of data storage structures are stacked and spaced apart from each other in the first direction.

A semiconductor device, comprising:

• a peripheral circuit structure comprising a peripheral circuit;
• a first stack structure and a second stack structure vertically overlapping the peripheral circuit structure and parallel to each other;
• and
• insulating separation pattern between the first stack structure and the second stack structure,
• wherein each of the first and second stack structures comprises word lines, active layers, bit lines, and data storage structures,
• wherein, for each of the first stack structure and the second stack structure, the word lines are stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the peripheral circuit structure,
• wherein, for each of the first stack structure and the second stack structure, the active layers are stacked and spaced apart from each other in the first direction, and comprising channel regions overlapping vertically the word lines,
• wherein, for each of the first stack structure and the second stack structure, each of the bit lines extends in the first direction and is connected to first sides of the active layers,
• wherein, for each of the first stack structure and the second stack structure, the data storage structure comprises first electrodes connected to second sides of the active layers, second electrodes spaced apart from the first electrodes, and a dielectric layer between the first electrodes and the second electrodes,
• wherein, for each of the first stack structure and the second stack structure, the second electrodes are stacked and spaced apart from each other in the first direction, and
• wherein, for each of the first stack structure and the second stack structure, the second electrodes of the first stack structure and the second electrodes of the second stack structure are in contact with the insulating separation pattern.