US 2024/0404946 A1Published application

Semiconductor storage device

AssigneeKioxia Corporation

InventorsYoshiyuki HORII, Hideo WADA

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Abstract

A semiconductor storage device includes a substrate, a first wiring layer, a second wiring layer, a memory cell array layer, and a first insulating layer. The memory cell array layer includes a plurality of first conductive layers that are arranged in a first direction, a first semiconductor layer that faces the plurality of first conductive layers, a first charge storage layer that is provided between the plurality of first conductive layers and the first semiconductor layer, and first and second contacts that extend in the first direction. The second wiring layer includes a second conductive layer that is connected to one end of the first semiconductor layer. The first wiring layer includes first and second electrodes that are connected to the first and second contacts. At least a part of surfaces of the first and second electrodes on a substrate side is closer to the substrate than a surface of the second conductive layer on the side opposite to the substrate in the first direction. A surface of the first electrode on the side opposite to the substrate includes a region that is not covered with the first insulating layer. A surface of the second electrode on the side opposite to the substrate is entirely covered with the first insulating layer.

Claims20

Dependent claims

A semiconductor storage device comprising:

a substrate;
a first wiring layer;
a second wiring layer disposed between the substrate and the first wiring layer;
a memory cell array layer disposed between the substrate and the second wiring layer;
and
a first insulating layer disposed on a side opposite to the substrate with respect to the first wiring layer,
wherein the memory cell array layer includes
a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate,
a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers,
a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer,
a first contact extending in the first direction, and
a second contact extending in the first direction,
the second wiring layer including a second conductive layer electrically connected to one end of the first semiconductor layer,
the first wiring layer includes
a first electrode electrically connected to the first contact, and
a second electrode electrically connected to the second contact,
at least a part of a surface of the first electrode on a substrate side and at least a part of a surface of the second electrode on the substrate side are closer to the substrate than a surface of the second conductive layer on the side opposite to the substrate in the first direction,
a surface of the first electrode on the side opposite to the substrate includes a region not covered with the first insulating layer, and
a surface of the second electrode on the side opposite to the substrate is entirely covered with the first insulating layer.

16 more elements

A semiconductor storage device comprising:

a substrate;
a first wiring layer;
a second wiring layer disposed between the substrate and the first wiring layer;
and
a memory cell array layer disposed between the substrate and the second wiring layer,
wherein the memory cell array layer includes
a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate,
a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers,
a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer,
a first contact extending in the first direction, and
a second contact extending in the first direction,
the second wiring layer includes
a second conductive layer electrically connected to one end of the first semiconductor layer, and
a first conductive member connected to one end of the second contact and having lengths in (i) a second direction intersecting the first direction and (ii) a third direction intersecting the first direction and the second direction that are smaller than lengths of the second conductive layer in the second direction and the third direction, respectively, and
the first wiring layer includes
a first electrode electrically connected to the first contact, and
another conductive layer separated from the first conductive member in the first direction and entirely covering a surface of the first conductive member on the side opposite to the substrate.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/664,536Filed 15 May 2024
Priority: JP 2023-08977331 May 2023
Published: 5 Dec 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 20/435
Characterised by their conductive parts: cross-sectional shapes or dispositions of interconnections
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels