Hemt power device with reduced gate oscillation and manufacturing process thereof

A process for manufacturing a heterojunction power device, comprising:

• on a substrate including semiconductor material, forming a first active area and a second active area symmetrically opposite with respect to an axis of symmetry, accommodating respective heterostructures and separated by a separation region, extending along the axis of symmetry;
• forming, on the separation region, a first conductive bus configured to distribute a first electric potential of the power device in parallel to the first and the second active areas;
• and
• forming, on the separation region, a second conductive bus configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas,
• wherein the first and the second conductive buses extend along the axis of symmetry, the second conductive bus overlying the first conductive bus.

A method, comprising:

• distributing a first electric potential from a first conductive bus in parallel to first transistor terminals of first active area and to first transistor terminals of a second active area, the first active area and a second active area arranged on the semiconductor substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures, the first conductive bus being positioned on a separation region extending along the axis of symmetry between the first active area and the second active area;
• and
• distributing a second electric potential from a second conductive bus in parallel to second transistor terminals of the first and the second active areas,
• wherein the first and the second conductive buses are stacked and extend along the axis of symmetry above the separation region.