Semiconductor package and method of manufacturing a semiconductor package

A semiconductor package, comprising:

• a redistribution structure having an upper surface and a lower surface opposing each other, wherein the redistribution structure includes a lower insulating layer, a plurality of redistribution layers disposed in the lower insulating layer, and a plurality of first vias connected to the plurality of redistribution layers, respectively;
• a semiconductor chip disposed on the upper surface of the redistribution structure and electrically connected to the plurality of redistribution layers;
• an interconnection structure disposed on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers disposed in the upper insulating layer, and a plurality of second vias connecting the plurality of interconnection layers to each other;
• an encapsulant covering at least a portion of each of the semiconductor chip and the interconnection structure on the upper surface of the redistribution structure;
• and
• a plurality of external connection conductors disposed on the lower surface of the redistribution structure and electrically connected to the plurality of redistribution layers,
• wherein a lowermost interconnection layer adjacent to the upper surface of the redistribution structure among the plurality of interconnection layers includes:
• a first conductive layer that contacts one second via of the plurality of second vias and is tapered toward the upper surface, and
• a second conductive layer that surrounds the first conductive layer and contacts one first via of the plurality of first vias.