Semiconductor package and manufacturing method thereof

A semiconductor package, comprising:

• a first redistribution layer including a plurality of wiring layers;
• a semiconductor die overlying the first distribution layer;
• an interlink block, disposed beside the semiconductor die and overlying the first redistribution layer, wherein the interlink block includes an encapsulant and a through insulation via extending through the encapsulant, and the through insulation via directly contacts at least one of the plurality of wiring layers of the first redistribution layer;
• and
• a molding compound disposed between the semiconductor die and the interlink block.

A manufacturing method for semiconductor packages, comprising:

• forming interlink blocks, wherein the interlink block includes through insulator vias laterally wrapped by an encapsulant;
• providing semiconductor dies over a first carrier with active surfaces of the semiconductor dies facing the first carrier;
• providing the interlink blocks on the first carrier and beside the semiconductor dies;
• forming a molding compound over the first carrier, encapsulating the semiconductor dies and the interlink blocks to form a molded structure;
• performing a first trimming process to the molded structure to expose the through insulator vias;
• forming a first redistribution layer over the semiconductor dies and the interlink blocks, wherein the first redistribution layer is electrically connected with the through insulator vias;
• attaching a second carrier to the first redistribution layer;
• detaching the first carrier from the molded structure;
• performing a second trimming process to the molded structure to expose the through insulator vias;
• and
• forming a second redistribution layer over the semiconductor dies and the interlink blocks, wherein the second redistribution layer is electrically connected with the through insulator vias.