Method of manufacturing semiconductor packages

A method of manufacturing a semiconductor package, the method comprising:

• providing a substrate comprising a plurality of semiconductor chips, each of the plurality of semiconductor chips comprising chip pads on a first surface of the semiconductor chip;
• forming a plurality of redistribution wiring layers on the first surface of the semiconductor chip, the plurality of redistribution wiring layers comprising redistribution wirings stacked in at least two layers of the plurality of redistribution wiring layers, the redistribution wiring being electrically connected to the chip pads;
• forming conductive bumps on an outer surface of the plurality of redistribution wiring layers;
• wherein the forming the plurality of redistribution wiring layers comprises:
• forming a first insulating layer;
• performing a first photo etching process on the first insulating layer to form first via holes;
• performing a second photo etching process on the first insulating layer to form second via holes;
• and
• forming first lower redistribution wirings on the first insulating layer, the first lower redistribution wirings being electrically connected to first bonding pads under the first insulating layer through the first via hole and the second via hole.

A method of manufacturing a semiconductor package, the method comprising:

• forming a first photoresist layer on a first insulating layer;
• forming a first photoresist pattern having first opening patterns using a first exposure mask;
• etching the first insulating layer using the first photoresist pattern as a first etching mask to form first via holes;
• removing the first photoresist pattern;
• forming a second photoresist layer on the first insulating layer;
• forming a second photoresist pattern having second opening patterns using a second exposure mask;
• etching the first insulating layer using the second photoresist pattern as a second etching mask to form second via holes;
• removing the first photoresist pattern;
• forming a redistribution wiring layer on the first insulating layer, the redistribution wiring layer having first redistribution wirings that are electrically connected to first bonding pads under the first insulating layer through the first via hole and the second via hole;
• and
• mounting a semiconductor chip on the redistribution wiring layer, the semiconductor chip comprising chip pads electrically connected to the first redistribution wirings.