Package structure and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Hung LIN, Shih-Peng TAI, Yu-Yi HUANG, Yu-Hao KUO
Life of this patent
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Abstract
A method for forming a package structure is provided, wherein the method includes forming an interconnect structure in a substrate. The method also includes bonding a chip over the substrate and electrically connected to the interconnect structure. The method includes bonding a plurality of dies over the substrate and adjacent to the chip. The method also includes supplying a molding material to the gap between the chip and the dies, after which the method includes thinning down the substrate.
Claims20
A method for forming a package structure, comprising:
- forming an interconnect structure in a substrate;
- bonding a chip over the substrate and electrically connected to the interconnect structure;
- bonding a plurality of dies over the substrate and adjacent to the chip;
- supplying a molding material to a gap between the chip and the dies;
- and
- after supplying the molding material to the gap between the chip and the dies, thinning down the substrate.
A method for forming a package structure, comprising:
- forming a plurality of through-substrate via (TSV) structures in a substrate;
- bonding a chip over a first surface of the substrate and electrically connected to a first plurality of the TSV structures;
- bonding a thermal-dissipation die over the first surface of the substrate and adjacent to the chip, wherein the thermal-dissipation die overlaps a second plurality of the TSV structures in a normal direction perpendicular to the first surface;
- supplying a molding material to a gap between the chip and the thermal-dissipation die;
- and
- thinning down the substrate from a second surface opposite the first surface.
A package structure, comprising:
- a substrate having a first surface and a second surface opposite the first surface;
- a plurality of through-substrate via (TSV) structures in the substrate, wherein a width of the TSV structures gradually decreases from the first surface to the second surface;
- a chip bonded to the first surface of the substrate;
- a plurality of dies bonded to the first surface of the substrate and located adjacent to the chip;
- a molding material between the chip and the dies;
- and
- a plurality of bump structures connected to the TSV structures on the second surface.
Dependencies are inferred from the claim text.