Chip complex with embedded interposer
AssigneeAdvanced Micro Devices, Inc.
InventorsDeepak Vasant KULKARNI, Raja SWAMINATHAN, Mihir PANDYA, Liwei WANG, Samuel NAFFZIGER
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Abstract
A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.
Claims20
An integrated circuit (IC) chip complex, comprising:
- a passive interposer, the passive interposer includes an interconnect formed in a back end of the line (BEOL) region;
- at least a first (IC) die of a first common tier hybrid bonded to a first side of the passive interposer;
- and
- at least two or more second (IC) dies of a second common tier hybrid bonded to a second side of the passive interposer.
An integrated circuit (IC) chip package, comprising:
- a substrate;
- and
- a chip complex mounted to the substrate, the chip complex comprising:
- a passive interposer;
- at least a first (IC) die of a first common tier hybrid bonded to a first side of the passive interposer;
- and
- at least two or more second (IC) dies of a second common tier hybrid bonded to a second side of the passive interposer.
A method for forming a chip complex comprising:
- securing a plurality of IC dies forming a first common tier to a temporary carrier substrate;
- hybrid bonding the IC dies of the first common tier to a first side of a passive interposer;
- thinning a second side of the passive interposer;
- hybrid bonding IC dies of a second common tier to the second side of the passive interposer;
- and
- removing the temporary carrier substrate.
Dependencies are inferred from the claim text.