Display device
AssigneeSamsung Display Co., Ltd.
InventorsMOO SOON KO, JEONG-SOO LEE, JUNG HWA KIM
Life of this patent
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Abstract
A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
Claims20
A display device comprising:
- a substrate including a display area and a peripheral area adjacent to the display area;
- at least one test element group disposed on the peripheral area of the substrate, and including a test TFT and a plurality of test pads electrically connected to the test TFT;
- first, second, and third dummy circuits disposed on the non-display area of the substrate,
- wherein each of the first, second, and third dummy circuits includes:
- a plurality of first dummy semiconductor layers;
- and
- a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers,
- wherein the first dummy circuit overlaps a first test pad of the plurality of test pads, and
- wherein one of the plurality of first dummy gate electrodes of the first dummy circuit overlaps a plurality of first dummy semiconductor layers of the first dummy circuit arranged in one line.
A display device comprising:
- a substrate including a display area and a peripheral area adjacent to the display area;
- at least one test element group disposed on the peripheral area of the substrate, and including a test TFT, a first test pad electrically connected to a test source electrode of the test TFT, a second test pad electrically connected to a test drain electrode of the test TFT, and a third test pad electrically connected to a test gate electrode of the test TFT,
- first, second, and third dummy circuits disposed on the non-display area of the substrate,
- wherein each of the first, second, and third dummy circuits includes:
- a plurality of first dummy semiconductor layers;
- and
- a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers,
- wherein the first dummy circuit overlaps a first test pad of the plurality of test pads, and
- wherein one of the plurality of first dummy gate electrodes of the first dummy circuit overlaps a plurality of first dummy semiconductor layers of the first dummy circuit arranged in one line.
Dependencies are inferred from the claim text.