Embedded stressors in epitaxy source/drain regions

A device comprising:

• a semiconductor fin;
• a gate stack over the semiconductor fin;
• a gate spacer on a sidewall of the gate stack;
• and
• a source/drain region aside of the gate spacer and comprising:
• a first semiconductor layer having a first phosphorous concentration;
• and
• a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second phosphorous concentration higher than the first phosphorous concentration, and the second semiconductor layer comprises:
• an upper portion contacting the gate spacer to form a vertical interface;
• and
• a lower portion lower than a top corner of the semiconductor fin;
• and
• a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer comprises phosphorous and has a third phosphorous concentration lower than the second phosphorous concentration.

A device comprising:

• a semiconductor substrate;
• isolation regions in the semiconductor substrate;
• a semiconductor fin higher than top surfaces of the isolation regions;
• a gate stack over a top surface and sidewalls of the semiconductor fin;
• and
• a source/drain region aside of the semiconductor fin, wherein the source/drain region comprises:
• a first semiconductor layer comprising a dopant having a first dopant concentration;
• a second semiconductor layer over and contacting the first semiconductor layer, wherein the second semiconductor layer comprises the dopant having a second dopant concentration higher than the first dopant concentration, and wherein the second semiconductor layer has an upper portion higher than the top surface of the semiconductor fin, and a lower portion lower than the top surface of the semiconductor fin;
• and
• a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer comprises the dopant having a third dopant concentration lower than the second dopant concentration.

A device comprising:

• a semiconductor fin;
• a gate stack over the semiconductor fin;
• and
• a source/drain region aside of the semiconductor fin, wherein the source/drain region comprises:
• a first semiconductor layer comprising a first top surface comprising a first facet;
• a second semiconductor layer over the first semiconductor layer and contacting the first facet to form a first interface, wherein the second semiconductor layer comprises a second top surface comprising a second facet;
• and
• a third semiconductor layer over the second semiconductor layer and contacting the second facet to form a second interface, wherein in a cross-sectional view of the device, the first interface and the second interface are joined at a same point.