Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

A semiconductor device, comprising:

• first and second source/drain features;
• first and second source/drain metal contacts formed above the first and second source/drain features;
• a gate electrode layer disposed between the first and second source/drain features;
• first and second sidewall spacers disposed between the gate electrode layer and the first and second source/drain metal contacts;
• a self-aligned contact (SAC) layer disposed above the gate electrode layer, wherein the SAC layer comprises a low-k dielectric material;
• a metal contact etch stop layer (M-CESL) disposed above the SAC layer;
• and
• a conductive feature having a first portion embedded in the M-CESL layer and a second portion in contact with the first source/drain metal contact, and the first portion of the conductive feature is in contact with the SAC layer.

A semiconductor device, comprising:

• a first source/drain feature;
• a gate structure adjacent the first source/drain feature;
• an interlayer dielectric (ILD) layer disposed over the first source/drain feature, wherein a top surface of the ILD layer is level with a top surface of the gate structure;
• a first source/drain metal contact formed through the ILD layer and in electrical contact with the first source/drain feature;
• and
• a low-k dielectric layer, wherein the low-k dielectric layer has a first portion disposed above the top surface of the ILD layer and a second portion disposed in the gate structure below the top surface of the gate structure.