Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
AssigneeLodestar Licensing Group LLC
InventorsKyle K. Kirby, Kunal R. Parekh, Sarah A. Niroumand
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Abstract
Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.
Claims20
A semiconductor device, comprising:
- a semiconductor substrate;
- a first layer comprising one or more first conductive portions between one or more first dielectric portions over the semiconductor substrate;
- a second layer comprising one or more second conductive portions between one or more second dielectric portions over the first layer;
- and
- a conductor extending through the semiconductor substrate, the conductor in contact with the one or more second conductive portions of the second layer and coupled with the one or more first conductive portions of the first layer through one or more vias.
A semiconductor device, comprising:
- a semiconductor substrate;
- a first layer comprising one or more first conductive traces between one or more first dielectric portions;
- an interconnect extending through the semiconductor substrate and comprising a first portion extending through the one or more first dielectric portions of the first layer and the semiconductor substrate;
- a second layer comprising one or more second dielectric portions over the one or more first dielectric portions and one or more second conductive traces between the one or more second dielectric portions, the one or more second conductive traces and electrically coupling the one or more first conductive traces and the interconnect, the one or more second conductive traces including a first portion vertically aligned with and electrically coupled with the interconnect at a second portion of the interconnect, wherein the one or more second dielectric portions have a first surface facing the one or more first dielectric portions and a second surface opposite the first surface, and wherein the second layer has a third surface coplanar with the second surface.
A semiconductor device, comprising:
- a semiconductor substrate;
- a first dielectric layer over the semiconductor substrate,
- a first conductive layer formed in the first dielectric layer;
- an interconnect comprising a first portion extending through the first dielectric layer and the semiconductor substrate;
- a second dielectric layer over the first dielectric layer;
- a second conductive layer formed in an opening of the second dielectric layer and having a first portion vertically aligned with and electrically coupled with the interconnect;
- a third dielectric layer over the second dielectric layer;
- and
- a third conductive layer formed in the third dielectric layer and at least partially vertically aligned with the second conductive layer, wherein the third conductive layer is electrically coupled with the second conductive layer through one or more vias, wherein the third dielectric layer includes a first surface facing the second dielectric layer and a second surface opposite the first surface, and wherein the third dielectric layer includes a third surface coplanar with the second surface of the third conductive layer.
Dependencies are inferred from the claim text.