Methods for isolation process control and structures thereof

An integrated circuit, comprising:

• a substrate having a first active region and a second active region separated by a dielectric isolation region;
• and
• a first fin in the first active region that comprises a longer first portion normal to the dielectric isolation region and a shorter second portion that parallels the dielectric isolation region;
• and
• a second fin in the second active region that comprises a longer first portion normal to the dielectric isolation region and a shorter second portion that parallels the dielectric isolation region;
• wherein the longer first portion of the first fin and the longer first portion of the second fin are in-line with each other;
• and
• wherein the shorter second portion of the first fin and the shorter second portion of the second fin are parallel to each other.

A method for forming a first active region and a second active region, comprising:

• forming a mandrel over a substrate;
• etching to form a trench in the mandrel;
• etching into the substrate to form a first fin and a third fin located in the first active region, a second fin and a fourth fin located in the second active region, and a plurality of shorter fins separating the first active region and the second active region;
• forming a fin etch mask that exposes the third fin and the fourth fin;
• etching to remove the third fin and the fourth fin;
• forming a CPODE mask that exposes the substrate between the plurality of shorter fins;
• etching into the substrate through the CPODE mask to form a trench;
• and
• filling the trench with a dielectric material to form an isolation region between the first active region and the second active region.