Molded direct contact interconnect substrate and methods of making same

A method of making a molded core substrate, comprising:

• providing a substrate core having at least one tracking identifier disposed therein and comprising at least one embedded component, wherein:
• the substrate core comprises one or more of:
• encapsulant, layers of glass fiber, a glass reinforced epoxy material such as FR4, CEM, plastic, polymer, mold compound such as epoxy or a thermoset material, a printed circuit board (PCB) with or without routing, a PCB core, metal, silicon, fiberboard, layers of paper laminated with epoxy or phenolic resin, carbon fiber, and composite, and
• the embedded component comprises one or more of:
• an active component, a chip, a die, a passive component, embedded capacitors, deep trench capacitors, inductors, bridge die, voltage regulators, RF components, optical components, opto-electronic components, conductive interconnects, and vertical interconnect blocks (VIB);
• forming a first patterned frontside conductive layer comprising at least one conductive trace, via, land, plane, line, and pad configured to be electrically coupled to the at least one embedded component over a front side of the substrate core;
• disposing a first frontside layer of encapsulant or dielectric over the front side of the substrate core, the at least one embedded component, and the first patterned frontside conductive layer;
• flipping the substrate core such that a back side of the substrate core is configured for processing;
• forming a first patterned backside conductive layer comprising at least one conductive trace, via, land, plane, line, and pad over the back side of the substrate core, the first patterned frontside conductive layer configured to be electrically coupled to the at least one embedded component;
• disposing a first backside layer of encapsulant or dielectric over the back side of the substrate core, over the at least one embedded component, and over the first patterned frontside conductive layer;
• planarizing the first backside layer of encapsulant by grinding, chemical mechanical polishing (CMP), surface planarization, polishing, plasma etching, wet etching, or thinning by using a diamond-based cutter, to expose at least a portion of the first patterned backside conductive layer to form a first backside planar surface on the first backside layer of encapsulant;
• forming a second patterned backside conductive layer over the first backside planar surface, the second patterned backside conductive layer configured to be electrically coupled to the first patterned frontside conductive layer;
• disposing a second backside layer of encapsulant over the second patterned backside conductive layer and the first backside planar surface;
• flipping the substrate core such that the first patterned frontside layer of encapsulant is configured for processing;
• planarizing the first patterned frontside layer of encapsulant to expose at least a portion of the first patterned frontside conductive layer to form a first frontside planar surface on the first frontside layer of encapsulant;
• forming a second patterned frontside conductive layer over the first frontside planar surface, the second patterned frontside conductive layer configured to be electrically coupled to the first patterned frontside conductive layer;
• disposing a second frontside layer of encapsulant over the second patterned frontside conductive layer and the first frontside planar surface;
• flipping the substrate core such that the second backside layer of encapsulant is configured for processing, and
• planarizing the second backside layer of encapsulant to expose at least a portion of the second patterned backside conductive layer to form a second backside planar surface on the second backside layer of encapsulant.