Dynamic bitscan for non-volatile memory

A method for operating non-volatile memory, the method comprising:

• applying a first verify reference voltage to a word line connected to a group of NAND memory cells that are organized as a plurality of bytes, wherein each byte of memory cells is grouped together physically within a block in a three-dimensional memory structure;
• sensing the group of memory cells in response to the first verify reference voltage;
• selecting a first strict subset of one or more bits in each of a subset of the plurality of bytes of memory cells;
• determining a first count of how many of the memory cells in the first strict subset meet a threshold voltage (Vt) criterion with respect to the first verify reference voltage, the first count being based on the sensing of the first strict subset;
• responsive to the first strict subset meeting the criterion with respect to the first verify reference voltage:
• selecting a second strict subset of one or more bits in each of the subset of the plurality of bytes of memory cells;
• and
• determining a second count how many of the memory cells in the second strict subset meet the Vt criterion with respect to the first verify reference voltage, the second count being based on the sensing of the second strict subset;
• applying a second verify reference voltage to the word line connected to the group of memory cells;
• sensing the group of memory cells in response to the second verify reference voltage;
• determining a third count of how many of the memory cells in the first strict subset meet a Vt criterion with respect to the second verify reference voltage;
• and
• responsive to the first strict subset not meeting the Vt criterion with respect to the second verify reference voltage:
• omitting counting of how many of the memory cells in the second strict subset meet the Vt criterion with respect to the second verify reference voltage.

A non-volatile storage system, comprising:

• a three-dimensional memory structure comprising blocks of memory cells arranged as NAND strings, the three-dimensional memory structure having bit lines extending over the blocks;
• and
• one or more control circuits in communication with the three-dimensional memory structure, the one or more control circuits configured to:
• apply a verify reference voltage to a group of memory cells in a selected block in the three-dimensional memory structure;
• perform a first bitscan of a first strict subset of the group of memory cells that each have a first distance in a bit line direction from an edge of the selected block;
• and
• perform a second bitscan of a second strict subset of the group of memory cells that each have a second distance in the bit line direction from the edge of the selected block responsive to a condition being met with respect to the first bitscan, wherein the second bitscan is not performed if the condition is not met.