Layout pattern for static random access memory

A layout pattern of a static random-access memory (SRAM), comprising:

• a substrate;
• four SRAM cell regions, which are arranged in a 2*2 array and form the layout pattern of the SRAM, wherein each SRAM cell region comprises:
• a plurality of fin structures are located on the substrate, and each fin structure extends along a second direction (Y direction);
• a plurality of gate structures are located on the substrate, and each gate structure extends along a first direction (X direction) and spans the plurality of fin structures to form a plurality of transistors, wherein the plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B;
• a first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line;
• a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, wherein the first word line contact pad and the second word line contact pad do not overlap in the second direction;
• a third word line contact pad connected to a gate of the third access transistor (PG2A) and the first word line;
• and
• a fourth word line contact pad connected to a gate of the fourth access transistor (PG2B) and the second word line, wherein the third word line contact pad and the fourth word line contact pad do not overlap in the second direction.