Memory Device Comprising Electrically Floating Body Transistor

A semiconductor memory instance comprising:

• an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:
• a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each include:
• a bipolar device having a floating base region, an emitter, and a collector,
• wherein said floating base region stores a state of said semiconductor memory cell,
• wherein said collector is connected to a buried well region,
• wherein said buried well region is common to said at least two of said semiconductor memory cells in one of said memory sub-arrays;
• wherein when a first semiconductor memory cell of said at least two of said semiconductor memory cells is in a first state and a second semiconductor memory cell of said at least two of said semiconductor memory cells is in a second state, application of a bias applied through said buried well region maintains said first semiconductor memory cell in said first state and said second semiconductor memory cell in said second state;
• wherein said states of said semiconductor memory cells are maintained upon repeated read operations;
• a first decoder circuit configured to select at least one of said at least one column or at least one of said at least one row;
• a second decoder circuit configured to select at least one of said at least two memory sub-arrays;
• and
• wherein said buried well region may be set to a first bias condition during a first memory operation and to a second bias condition during a second memory operation.