Memory device and method of operating the same

A memory device comprising:

• a memory cell array comprising a first bank and a second bank comprising a plurality of memory cell rows;
• a row hammer management circuit configured to perform a first read-modify-write (RMW) operation with respect to the first bank and a second RMW operation with respect to the second bank in parallel;
• and
• an RMW driver configured to generate a first RMW core signal group and a second RMW core signal group in parallel, the first RMW core signal group controlling the first RMW operation with respect to the first bank and the second RMW core signal group controlling the second RMW operation with respect to the second bank, wherein the first RMW core signal group is generated based on a first precharge command with respect to the first bank and the second RMW core signal group is generated based on a second precharge command with respect to the second bank, a first precharge operation corresponding to the first precharge command is performed after a time delay by an active count update time from a time point where the first precharge command is applied, and a second precharge operation corresponding to the second precharge command is performed after a time delay by the active count update time from a time point where the second precharge command is applied.

A method of operating a memory device, comprising:

• receiving an active command corresponding to a target memory cell row among a plurality of memory cell rows;
• receiving a precharge command corresponding to the target memory cell row;
• generating, based on the precharge command, an internal active count update signal corresponding to the target memory cell row;
• generating, based on the internal active count update signal, a plurality of control signals that update count data with respect to the target memory cell row;
• and
• performing, based on the precharge command, a precharge operation on the target memory cell row after an active count update time is elapsed.