Multi-die memory device
AssigneeRambus Inc.
InventorsScott C. Best, Ming Li
Life of this patent
Estimating the term…
Abstract
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
Claims21
(canceled)
A logic integrated circuit (IC) base die for a three-dimensional memory device, comprising:
- an engagement surface to mount multiple memory die that are configured as a memory stack, the multiple memory die comprising multiple independent memory interfaces;
- a primary interface to communicate with memory control circuitry;
- and
- multiple independent secondary interfaces, each of the multiple independent secondary interfaces configured to couple to a corresponding one of the multiple independent memory interfaces of the multiple memory die in a dedicated manner.
A base layer for a three-dimensional memory device, comprising:
- an active substrate comprising
- an engagement surface to mount multiple dynamic random access memory (DRAM) die that are configured as a memory stack, the multiple DRAM die comprising multiple independent DRAM memory interfaces;
- a primary interface for communicating with DRAM memory control circuitry;
- and
- multiple independent secondary interfaces, each of the multiple independent secondary interfaces configured to couple to a corresponding one of the multiple independent DRAM memory interfaces of the multiple DRAM die in a dedicated manner.
A method of operation in a logic integrated circuit (IC) base die of a three-dimensional memory device, the method comprising:
- communicating with a memory controller via a primary interface of the logic IC base die, the logic IC base die including multiple independent secondary interfaces;
- communicating with a memory stack of multiple memory die via multiple independent secondary interfaces of the logic IC base die;
- and
- performing data transfers between the logic IC base die and the multiple memory die, the data transfers performed in a dedicated manner between at least one independent memory interface of each of the multiple memory die and a corresponding one of the multiple independent secondary interfaces of the logic IC base die.
Dependencies are inferred from the claim text.