Systems and Methods for a Power Wake-Up Sequence In a Memory Device

A method for controlling a wake-up operation for a memory array that includes a plurality of memory cells, comprising:

• receiving a primary sleep signal indicating an initiation of the wake-up operation;
• pre-charging a first memory cell in response to the primary sleep signal;
• generating, at a first buffer, a delayed primary sleep signal in response to the primary sleep signal;
• generating a looped sleep signal based on the delayed primary sleep signal;
• generating, at first logic circuitry, a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, the first bit line pre-charge signal being generated in response to the looped sleep signal;
• and
• pre-charging one or more bit line of the first memory cell in response to the first bit line pre-charge signal.

A method for controlling a wake-up operation for a memory array that includes a plurality of memory cells, comprising:

• providing a primary sleep signal to pre-charge one or more memory cells;
• generating a first bit line pre-charge signal for a first memory cell from a signal derived from the primary sleep signal;
• and
• providing the first bit line pre-charge signal to pre-charge one or more bit line of the first memory cell,
• wherein the first bit line pre-charge signal is delayed from the primary sleep signal to the extent that the one or more bit line is not pre-charged until after the first memory cell has been completely pre-charged.