Memory device having non-uniform refresh
AssigneeRambus Inc.
InventorThomas Vogelsang
Life of this patent
Estimating the term…
Abstract
An integrated circuit memory device is disclosed. The memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.
Claims21
(canceled)
An integrated circuit (IC) memory controller to control an IC memory device, the IC memory device including an array of storage cells configured into multiple banks, each bank comprising multiple segments, each of the multiple segments accessible via a bank address and a segment address, the IC memory controller comprising:
- command generation circuitry to generate per-segment values representing per-segment refresh rates for self-refresh logic in the IC memory device;
- and
- interface circuitry to transmit the per-segment values representing the per-segment refresh rates to the IC memory device, the IC memory device disposed external to the IC memory controller.
A method of operation in an integrated circuit (IC) memory controller, the IC memory controller to control an IC memory device, the IC memory device including an array of storage cells configured into multiple banks, each bank comprising multiple segments, each of the multiple segments accessible via a bank address and a segment address, the method comprising:
- generating, with command generation circuitry, per-segment values representing per-segment refresh rates for self-refresh logic in the IC memory device;
- and
- transmitting, with interface circuitry, the per-segment values representing the per-segment refresh rates to the IC memory device, the IC memory device disposed external to the IC memory controller.
An integrated circuit (IC) chip, comprising:
- dynamic random access memory (DRAM) control circuitry to control an IC DRAM memory device, the IC DRAM memory device including an array of DRAM storage cells configured into multiple banks, each bank comprising multiple segments, each of the multiple segments accessible via a bank address and a segment address, the DRAM control circuitry comprising:
- a command generator to generate per-segment values representing per-segment refresh rates for self-refresh logic in the IC DRAM memory device;
- and
- input/output (I/O) circuitry to transmit the per-segment values representing the per-segment refresh rates to the IC DRAM memory device, the IC DRAM memory device disposed external to the IC chip.
Dependencies are inferred from the claim text.