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US 2024/0404573 A1Published application
Semiconductor devices for calibrating phase of division clock
AssigneeSK hynix Inc.
InventorChang Hyun KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a command decoder configured to generate a block command, based on a command address, and a clock division circuit configured to divide an internal clock and an inverted internal clock to generate division clocks. In the present disclosure, the clock division circuit is configured to stop generating the division clocks for a block section when the block command is generated.
Claims20
A semiconductor device comprising:
- a command decoder configured to generate a block command, based on a command address;
- and
- a clock division circuit configured to divide an internal clock and an inverted internal clock to generate division clocks,
- wherein the clock division circuit is configured to stop generating the division clocks for a block section when the block command is generated.
1 more element
A semiconductor device comprising:
- a clock latch circuit configured to latch an internal clock and an inverted internal clock, based on a block control pulse to generate a first division clock, a second division clock, a third division clock, a fourth division clock, and a latch clock;
- and
- a block control pulse generating circuit configured to sequentially latch a block command, based on the third division clock and the latch clock to generate the block control pulse,
- wherein the clock latch circuit is configured to stop generating the first division clock, the second division clock, the third division clock, and the fourth division clock for a block section in which the block control pulse is generated.
1 more element
Dependencies are inferred from the claim text.