Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption

A memory system comprising:

• a memory device including a plurality of memory cells;
• and
• a memory controller configured to transmit a first command and a clock signal to the memory device to control the memory device,
• wherein the memory controller is configured to switch a frequency of the clock signal to a first frequency according to assertion of a status signal provided from the memory device that indicates an operation status of the memory device according to the command, and switch the frequency of the clock signal to a second frequency different from the first frequency according to de-assertion of the status signal,
• when the first command is a read command, the memory device is configured to receive the clock signal having the first frequency that is toggled at a low frequency while reading data stored in memory cells of the memory device, and transmit the clock signal having the second frequency that is toggled at a high frequency while transmitting the read data to the memory controller.

A method of providing a clock signal, the method comprising:

• determining, by a memory controller, a first command for an operation condition of a memory device;
• performing, by the memory device, a first operation in response to the first command, wherein the first operation includes a read operation or a write operation of the memory device, and a frequency of the clock signal is set to be relatively higher when the memory device performs the read operation than when the memory device performs the write operation;
• asserting, by the memory device, a status signal indicating a status of the first operation;
• switching, by the memory controller, a frequency of the clock signal to a first frequency
• in response to the assertion of the status signal;
• de-asserting, by the memory device, the status signal;
• and
• switching, by the memory controller, the frequency of the clock signal to a second frequency different from the first frequency according to the de-assertion of the status signal.