Low power memory with on-demand bandwidth boost

An integrated-circuit memory component (memory IC) comprising:

• a clock input to receive a clock signal;
• a programmable register;
• a command interface to receive a register-programming command synchronously with respect to the clock signal and, in response to the register-programming command, to store within the programmable register a control value that specifies one of a plurality of operating modes;
• and
• a synchronous data interface to:
• sample a write data signal in a first mode to generate a first quantity of write data bits per cycle of the clock signal if the control value specifies a first operating mode;
• sample the write data signal in a second mode to generate a second quantity of write data bits per cycle of the clock signal if the control value specifies a second operating mode, the second quantity of data bits exceeding the first quantity of data bits;
• and
• transmit a read data signal synchronously with respect to the clock signal.

A method of operation within integrated-circuit memory component (memory IC), the method comprising:

• receiving a clock signal via a clock input;
• receiving, via a command interface, a register-programming command synchronously with respect to the clock signal;
• storing a control value within the programmable register in response to the register-programming command, the control value specifying one of a plurality of operating modes;
• and
• sampling a write data signal, received via a synchronous data interface, in a first mode to generate a first quantity of write data bits per cycle of the clock signal if the control value specifies a first operating mode;
• sampling the write data signal in a second mode to generate a second quantity of write data bits per cycle of the clock signal if the control value specifies a second operating mode, the second quantity of data bits exceeding the first quantity of data bits;
• and
• transmitting a read data signal via the synchronous data interface synchronously with respect to the clock signal.

An integrated-circuit memory component (memory IC) comprising:

• a programmable register;
• means for receiving a clock signal;
• means for receiving a register-programming command synchronously with respect to the clock signal and, in response to receiving the register-programming command, for storing within the programmable register a control value that specifies one of a plurality of operating modes;
• and
• a synchronous data interface having:
• means for sampling a write data signal in a first mode to generate a first quantity of write data bits per cycle of the clock signal if the control value specifies a first operating mode;
• means for sampling the write data signal in a second mode to generate a second quantity of write data bits per cycle of the clock signal if the control value specifies a second operating mode, the second quantity of data bits exceeding the first quantity of data bits;
• and
• means for transmitting a read data signal synchronously with respect to the clock signal.