Memory system performing hierarchical duty cycle adjuster training and duty cycle adjuster training method thereof

A memory system configured to adjust duty cycle of four internal clock signals through a duty cycle adjuster (DCA) code, comprising:

• a memory device configured to generate a data signal or a data strobe signal with duty cycle changes in response to the DCA code;
• and
• a memory controller configured to perform hierarchical DCA training on the memory device to select an improved DCA code and set the memory device using the improved DCA code,
• wherein the memory controller is configured to perform a first DCA training step on the memory device using first DCA code combinations with a first offset size to adjust the duty cycle of each of the internal clock signals, and to perform a second DCA training step on the memory device using second DCA code combinations with a second offset size under conditions in which the memory device is set according to a result of the first DCA training step.

A method of training a memory device, comprising:

• performing first duty cycle adjuster (DCA) training on the memory device using first DCA code combinations with a first offset size to adjust the duty cycle of each of a plurality of internal clock signals;
• and
• performing second DCA training on the memory device using second DCA code combinations with a second offset size under conditions in which the memory device is set according to a results of the first DCA training,
• wherein a maximum value of the first offset size is greater than maximum value of the second offset size, and the method includes calculating scores based on eye window size of data signal corresponding to each of the first to second DCA code combinations in the first to second DCA training.