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US 2024/0404566 A1Published application
Header layout design including backside power rail
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHaruki MORI, Chien-Chi TIEN, Chia-En HUANG, Hidehiro FUJIWARA, Yen-Huei CHEN, Feng-Lun CHEN
Life of this patent
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Abstract
Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
Claims20
A header circuitry comprising a plurality of switching devices, the header circuitry comprising:
- a first region of a first conductivity type;
- a first section in the first region comprising a first backside power rail (BPR) disposed in a first direction, the first BPR comprising a first voltage source providing a first voltage;
- a second section in the first region comprising a second BPR disposed in the first direction, the second BPR comprising a second voltage source providing a second voltage that is different from the first voltage;
- a second region of a second conductivity type disposed in the first direction adjacent the first region of the first conductivity type, the second region comprising a third BPR disposed in the first direction and comprising a third voltage source providing a third voltage that is different from the first and the second voltages;
- a diffusion region disposed in a second direction and extending over the second BPR in the second section and the third BPR in the second region;
- a connection between the diffusion region and the second BPR to provide the second voltage of the second voltage source to the second region;
- and
- poly gate lines disposed in the second direction and extending over the third BPR in the second region.
5 more elements
A memory device, comprising:
- a memory array;
- and
- a header circuitry comprising a plurality of switching devices operably connected to the memory array, the header circuitry comprising:
- a first region of a first conductivity type;
- a first section in the first region comprising a first backside power rail (BPR) disposed in a first direction, the first BPR comprising a first voltage source providing a first voltage;
- a second section in the first region comprising a second BPR disposed in the first direction, the second BPR comprising a second voltage source providing a second voltage that is different from the first voltage;
- a second region of a second conductivity type disposed in the first direction adjacent the first region of the first conductivity type, the second region comprising a third BPR disposed in the first direction and comprising a third voltage source providing a third voltage that is different from the first and the second voltages;
- a diffusion region disposed in a second direction and extending over the second BPR in the second section and the third BPR in the second region;
- a connection between the diffusion region and the second BPR to provide the second voltage of the second voltage source to the second region;
- and
- poly gate lines disposed in the second direction and extending over the third BPR in the second region.
8 more elements
An electronic device, comprising:
- a processing device;
- and
- a memory device operably connected to the processing device, wherein the processing device is operable to control operations of the memory device, the memory device comprising:
- a memory array;
- and
- a header circuitry comprising a plurality of switching devices operably connected to the memory array, the header circuitry comprising:
- a first region of a first conductivity type;
- a first section in the first region comprising a first backside power rail (BPR) disposed in a first direction, the first BPR comprising a first voltage source providing a first voltage;
- a second section in the first region comprising a second BPR disposed in the first direction, the second BPR comprising a second voltage source providing a second voltage that is different from the first voltage;
- a second region of a second conductivity type disposed in the first direction adjacent the first region of the first conductivity type, the second region comprising a third BPR disposed in the first direction and comprising a third voltage source providing a third voltage that is different from the first and the second voltages;
- a diffusion region disposed in a second direction and extending over the second BPR in the second section and the third BPR in the second region;
- a connection between the diffusion region and the second BPR to provide the second voltage of the second voltage source to the second region;
- and
- poly gate lines disposed in the second direction and extending over the third BPR in the second region.
11 more elements
Dependencies are inferred from the claim text.