Shift Register, Gate Driving Circuit, Display Apparatus and Driving Method

A shift register, comprising:

• a first input sub-circuit, connected to a first input signal line and coupled to a first pull-up node;
• a second input sub-circuit, connected to a second input signal line and coupled to the first pull-up node;
• and
• an output sub-circuit, configured to output an output signal via an output terminal under control of the first pull-up node;
• a display reset sub-circuit, connected to the first pull-up node and connected to a third signal line, wherein a control terminal of the display reset sub-circuit is connected to a display reset control terminal;
• a pull-down control sub-circuit, configured to control a potential of a pull-down node according to the first pull-up node;
• and
• a pull-down sub-circuit, configured to pull down the first pull-up node and the output terminal to a non-operating potential under control of the pull-down node, and comprising a pull-down control transistor having an electrode connected to a first signal line,
• wherein,
• the first input sub-circuit comprises a charging sub-circuit, a storing sub-circuit, and an isolating sub-circuit, wherein
• the charging sub-circuit comprises a charging transistor, having a first electrode and/or control electrode connected to a first input terminal, and a second electrode connected to a blanking pull-up control node;
• the storing sub-circuit comprises a first capacitor, having a first terminal connected to the blanking pull-up control node;
• and
• the isolating sub-circuit comprises a first isolating transistor, wherein a control terminal of the first isolating transistor is connected to the blanking pull-up control node, and an electrode of the first isolating transistor is connected to the output terminal of the first input sub-circuit;
• the second input sub-circuit comprises:
• a display input transistor, wherein a first electrode of the display input transistor and a control electrode of the display input transistor are connected with each other, and a second electrode of the display input transistor is connected to the first pull-up node;
• the output sub-circuit comprises:
• a first output transistor, wherein a first electrode of the first output transistor is connected to a fourth clock signal line, a second electrode of the first output transistor is connected to a first output terminal, and a control electrode of the first output transistor is connected to the first pull-up node;
• and
• an output capacitor, wherein a first electrode of the output capacitor is connected to the first pull-up node, and a second electrode of the output capacitor is connected to the first output terminal.