Ray-Box Intersection Circuitry
AssigneeApple Inc.
InventorsChristopher A. Burns, Casper R. van Benthem
Life of this patent
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AssigneeApple Inc.
InventorsChristopher A. Burns, Casper R. van Benthem
Estimating the term…
Techniques are disclosed relating to ray intersection tests for ray tracing in graphics processors. In some embodiments, a ray cache stores, transformed ray direction corresponding to a transform of a ray based on its dominant direction axis. Ray intersect acceleration circuitry may determine whether a ray intersects a bounding volume of a bounding volume hierarchy (BVH) data structure. Ray-plane test circuitry may perform a set of six ray-plane tests for the bounding volume using at most four floating-point multiplication operations by four multiplier circuits. The floating-point operations may operate on the transformed ray direction components from the ray cache circuitry and coordinate information for the bounding volume. Disclosed techniques may reduce area and power consumption by avoiding multiplier circuitry for some ray-plane tests.
An apparatus, comprising:
A method, comprising:
A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:
Dependencies are inferred from the claim text.