System and method for generation of a network using physical awareness data from an image of a chip floorplan
AssigneeArteris, Inc.
InventorsChristopher PEZLEY, Xavier VAN RUYMBEKE, Simon MONTEIRO, Amir CHARIF
Life of this patent
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Abstract
Floorplanning for a semiconductor chip includes loading an image of a first floorplan of the chip; converting the digital image to a grayscale image; detecting blockages in the grayscale image; and generating a second floorplan corresponding to the first floorplan. The second floorplan shows representations of the blockages and maximum available area for a network-on-chip (NoC).
Claims18
A computer-implemented method for floorplanning of a semiconductor chip, the method comprising:
- loading a digital image of a first floorplan of the chip;
- converting the digital image to a grayscale image;
- detecting blockages in the grayscale image;
- and
- generating a second floorplan corresponding to the first floorplan, the second floorplan showing representations of the blockages and maximum available area for a network-on-chip (NoC).
A computer system comprising a processor and computer memory configured with a chip floorplanning tool for loading a digital image of a first floorplan of a semiconductor chip;
- converting the digital image to a grayscale image;
- detecting blockages in the grayscale image;
- and generating a second floorplan corresponding to the first floorplan, the second floorplan showing the blockages and maximum available area for a network-on-chip (NoC).
A non-transitory computer-readable memory configured with instructions that, when executed, cause a processor to:
- load a digital image of a first floorplan of a semiconductor chip;
- convert the digital image to a grayscale image;
- detect blockages in the grayscale image;
- and
- generating a second floorplan corresponding to the first floorplan, the second floorplan showing representations of the blockages and maximum available area for a network-on-chip (NoC).
Dependencies are inferred from the claim text.