Design tool for automated placement constraint generation, adapter insertion process, and local and global congestion capture
AssigneeArteris, Inc.
InventorsAmir CHARIF, Xavier VAN RUYMBEKE, Devin BRIGHT
Life of this patent
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AssigneeArteris, Inc.
InventorsAmir CHARIF, Xavier VAN RUYMBEKE, Devin BRIGHT
Estimating the term…
A tool is disclosed that automatically generates constraints for the placement of network elements, which can be understood by the backend tools that follow the constraints. The tool also constrains the placement within given bounds results in faster runtimes in the backend tools. Further, the tool automatically inserts additional elements into the topology to help with timing closure in downstream or backend tools. Additionally, the tool provides real-time feedback on wire congestion to the user during editing. The tool also implements a machine learning model that is trained and receives feedback for solutions provided to further train the model. The tool also includes the ability to use feedback to train a machine learning model for automated and assisted topology analysis and synthesis. The tool generates physical implementation guidance, which is during physical implementation of the synthesized NoC.
A method for guiding physical generation of a network-on-chip (NoC), the method comprising:
A design tool for generating a network-on-chip (NoC) topology within a floorplan, the tool comprising a region builder unit that allows generation of a polygon shaped regions that avoid blockage areas in the floorplan and optimize each region.
Dependencies are inferred from the claim text.