Zero diffusion break between standard cells using three-dimensional cross field effect self-aligned transistors

A method comprising:

• forming a plurality of standard cells with one or more of the standard cells comprising non-planar transistors by:
• forming, in an integrated circuit of at least one of the one or more of the standard cells, a first transistor with a first channel oriented in a first direction;
• forming, in the integrated circuit, an oxide layer adjacent to the first transistor;
• forming, in the integrated circuit, a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction;
• and
• arranging, in an integrated circuit, the plurality of standard cells, wherein each of a plurality of metal gates, within at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate.

A processor comprising:

• a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
• and
• computing core circuitry configured to execute the instructions of the one or more tasks using the source data;
• and
• wherein the computing core circuitry includes an integrated circuit comprising:
• a plurality of standard cells, one or more of the standard cells comprising non-planar transistors;
• wherein each of a plurality of metal gates, within at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate.