Operation verification system and operation verification device

An operation verification system comprising:

• an FPGA having a circuit programmed therein;
• an internal RAM of the FPGA;
• a bus circuit interposed for transmission and reception of data between the internal RAM and outside;
• an external memory of the FPGA in which a node value of the FPGA is written from the internal RAM via the bus circuit;
• a computer having installed therein a simulator which simulates the circuit;
• and
• a communication path connecting the FPGA and the computer via the bus circuit, wherein
• the computer includes a system memory in which an internal state value when the simulator is operated is written, and a control unit which controls the FPGA via the communication path,
• the control unit includes an operation instruction unit for operating the circuit and the simulator, and a comparison unit which compares the node value when the circuit is operated, obtained from the external memory and the internal state value corresponding to the node value, to verify operation of the FPGA, and
• the operation instruction unit operates the circuit and the simulator at the same time.