Interface clock management
AssigneeRambus Inc.
InventorYuanlong WANG
Life of this patent
Estimating the term…
Abstract
The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
Claims21
(canceled)
A memory device, comprising:
- a flash memory core;
- a clock receiver circuit to receive a clock signal;
- a parallel receiver circuit to receive flash memory commands comprising a plurality of bits synchronously with respect to the clock signal, the flash memory commands including a read command that specifies an access of data from the flash memory core;
- a serial driver circuit to transmit status information pertaining to the access of data from the flash memory core;
- a plurality of output drivers to output the data, in parallel, after a delay time that transpires from when the read command is received at the parallel receiver circuit;
- and
- a first output driver to output a signal, before the data is ready to be output by the plurality of output drivers, that indicates whether the memory device is to receive the clock signal.
A memory device, comprising:
- a flash memory core;
- an input to receive a clock signal;
- a plurality of receivers to receive, in parallel and associated with a transaction, a corresponding plurality of commands bits synchronously with respect to the clock signal;
- a first driver to serially transmit, synchronously with respect to a toggling version of the clock signal, status information associated with the transaction;
- and
- a second driver to assert a clock resume signal that indicates, to a controller, whether the memory device is to receive the toggling version of the clock signal.
A method of operating a memory device, comprising:
- receiving, from a controller, a toggling version of a clock signal;
- receiving, from the controller, a non-toggling version of the clock signal;
- receiving, from a controller, a command, timed by the toggling version of a clock signal, to access a flash memory core;
- transmitting, collectively with another memory device, a first indicator to the controller that the memory device is ready to receive the non-toggling version of the clock signal;
- and
- transmitting, collectively with the another memory device, a second indicator to the controller that the memory device is ready to receive the toggling version of the clock signal to time a data transfer.
Dependencies are inferred from the claim text.