A/d converter control circuit

An A/D conversion control circuit comprising:

• a scan group control unit controlling a plurality of AD conversion channels with a plurality of scan groups having different priorities;
• and
• a FIFO unit provided corresponding to each of the plurality of scan groups, each having a plurality of FIFO memories that sequentially stores an output from the scan group control unit for each corresponding scan group,
• wherein the scan group control unit includes:
• an input reception unit receiving an AD conversion channel of a corresponding scan group among the plurality of AD conversion channels according to an instruction, and outputting it to the corresponding FIFO memory;
• and
• an arbitration unit determining timing of conversion start, interruption, and restart in each of the plurality of scan groups,
• wherein the FIFO unit further includes a plurality of pointer control units provided correspondingly to the plurality of FIFO memories, respectively, and
• wherein each of the pointer control units clears or changes a position of a write pointer/read pointer of the corresponding FIFO memory at the timing of at least any of the start, interruption, and/or restart of the corresponding scan group according to the priority of the scan group.