Local internal discovery and configuration of individually selected and jointly selected devices
AssigneeRambus Inc.
InventorJohn Eric Linstadt
Life of this patent
Estimating the term…
Abstract
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.
Claims21
(canceled)
A memory controller for controlling a first memory device having an array of memory cells for storing data, the memory controller comprising:
- a command/address interface to transmit a connectivity read command to the first memory device over a command/address link;
- a data interface to receive a predetermined bit pattern over a data link from the first memory device in response to the connectivity read command;
- and
- connectivity discovery logic to determine a connectivity state between the memory controller and the first memory device based on the predetermined bit pattern, and to configure the memory controller for communicating with the first memory device based on the connectivity state.
A method for operating a memory controller configured to control a first memory device having an array of memory cells, the method comprising:
- transmitting a connectivity read command to the first memory device over a command/address link;
- receiving at a data interface, a predetermined bit pattern from the first memory device in response to the connectivity read command;
- determining a connectivity state between the memory controller and the first memory device based on the predetermined bit pattern received at the data interface;
- and
- configuring the memory controller for communicating with the first memory device based on the connectivity state.
A memory controller for controlling a memory device having an array of memory cells for storing data, the memory controller comprising:
- a command/address interface to transmit a predetermined bit sequence to the memory device over a command/address link;
- a data interface to receive a plurality of bit patterns from the memory device, each bit pattern received corresponding to a subset of bit values from the predetermined bit sequence, each bit pattern having a single bit representing a first logic state to indicate connectivity of a unique data pin of the memory device and remaining bits other than the single bit in the bit pattern representing a second logic state;
- and
- a circuit to determine a connectivity configuration of each pin of a data interface of the memory device based on the plurality of bit patterns received by the data interface of the memory controller.
Dependencies are inferred from the claim text.