System and method for valid window maximization in toggle mode link using systematic skew addition to compensate for sso and crosstalk

A non-transitory computer-readable storage medium comprising instructions executable by a processor, the instructions programming the processor to control a first circuit and at least one second circuit that communicate with each other through a parallel interface, wherein the first circuit is configured to transfer data signals (DQ signals) and strobe signals (DQS) to the at least one second circuit over one or more data lines of the parallel interface, the instructions programming the processor to, for each respective second circuit:

• calculate a valid window of each DQ signal transferred to the respective second circuit;
• identify from the DQ signals at least one critical signal having a smallest valid window;
• set a reference valid window to the smallest valid window;
• determine whether each respective valid window satisfies a condition of being less than the reference valid window plus a valid window margin;
• when a respective valid window satisfies the condition, store the DQ signal corresponding to the respective valid window in a Critical Timing (CT) bucket;
• when a respective valid window does not satisfy the condition, store the DQ signal corresponding to the respective valid window in a Relaxed Timing (RT) bucket;
• skew each DQ signal placed in the CT bucket by a skew amount together and measure the valid window of the respective DQ signal again;
• when the valid window after the respective DQ signal is skewed is equal to an initial valid window of the respective DQ signal, store the valid window as the maximum valid window;
• store skew tap settings with the maximum valid window for write training taps for a respective second circuit;
• and
• derive DQS tap settings based on the respective valid windows of the one or more DQ signals stored in the CT bucket.

A method for operating a device comprising a first circuit and at least one second circuit that communicate with each other through a parallel interface, wherein the first circuit is configured to transfer data signals (DQ signals) and strobe signals (DQS) to the at least one second circuit over one or more data lines of the parallel interface, the method comprising:

• calculating a valid window of each DQ signal transferred to a respective second circuit;
• identifying from the DQ signals one or more critical signals having a smallest valid window plus a valid window margin;
• storing the one or more critical signals in a Critical Timing (CT) bucket;
• storing other DQ signals in a Relaxed Timing (RT) bucket;
• skewing the one or more critical signals stored in the CT bucket by a skew amount together;
• continuing to skew and measure the valid window of the one or more critical signals until a maximum valid window is obtained;
• storing skew tap settings with the maximum valid window for the one or more critical signals for write training taps for a respective second circuit;
• and
• deriving DQS tap settings based on the respective valid windows of the one or more critical signals stored in the CT bucket.