Techniques for efficient pre-fetch data buffer management by a memory controller
AssigneeNVIDIA Corporation
InventorManikandan SUBRAMANIAN
Life of this patent
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AssigneeNVIDIA Corporation
InventorManikandan SUBRAMANIAN
Estimating the term…
Various embodiments include techniques for managing pre-fetch data in a computing system. A memory controller receives pre-fetch operations from a pre-fetch generator associated with a processing unit. The pre-fetch operations identify data that is likely to be accessed by the processing unit in the near future. In response, the memory controller retrieves read data associated with the read operations from system memory and stores the read data in a pre-fetch buffer included in the memory controller. The memory controller further receives status data via a low-latency signal path. The status data indicates information about each read operation, such as if the read operation can be serviced by a cache memory and whether the read operation is delayed but is to be transmitted to the memory controller. In response, the memory controller purges data from or holds data in the pre-fetch buffer based on the status data.
A computer-implemented method for managing pre-fetch data in a computing system, the method comprising:
A system, comprising:
Dependencies are inferred from the claim text.