Devices using chiplet based storage architectures
AssigneeSK hynix Inc.
InventorsIe Ryung PARK, Dong Sop LEE
Life of this patent
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Abstract
A device for implementing a storage architecture includes a front-end chip having at least one front-end link, and at least one back-end chip having back-end link for communication with the front-end link. The front-end link and the back-end link include a link layer and a physical layer, respectively. A data packet that is transmitted between the front-end link and the back-end link is composed of at least one flow control digit, and the flow control digit is composed of at least one physical digit. The link layer is configured to process data in the form of separating the flow control digit into upper layer data and flow control data. And the physical layer is configured to process data in the form of a data packet part and a control packet part.
Claims20
A device for implementing a storage architecture, comprising:
- a front-end chip including at least one front-end link;
- and
- at least one back-end chip including back-end link for communication with the front-end link,
- wherein the front-end link and the back-end link includes a link layer and a physical layer, respectively,
- wherein a data packet that is transmitted between the front-end link and the back-end link is composed of at least one flow control digit,
- wherein the flow control digit is composed of at least one physical digit,
- wherein the link layer is configured to process data in a form of separating the flow control digit into upper layer data and flow control data, and
- wherein the physical layer is configured to process data in the form of a data packet part and a control packet part.
Dependencies are inferred from the claim text.