Aggregation of multiple memory modules for a system-on-chip

An integrated circuit comprising:

• a substrate comprising a first circuit;
• a second circuit comprising at least a first memory interface, the second circuit being configured to be a first die disposed on the substrate, wherein the first memory interface is configured to couple to the first circuit;
• a third circuit comprising a second memory interface, the third circuit being configured to be a second die disposed on the substrate adjacent to the first die, wherein the second memory interface is configured to couple to the first circuit;
• and
• multiple memory circuits disposed on the second die, each of the multiple memory circuits at least partially sharing the second memory interface to communicate with the second circuit via the first circuit and the first memory interface.

A method of coupling a system-on-chip circuit to separate memory circuits, the method comprising:

• providing a substrate comprising a first circuit;
• providing a second circuit comprising a first memory interface;
• disposing the second circuit on the substrate, the first memory interface being configured to couple to the first circuit;
• providing at least a third circuit comprising a second memory interface, the second memory interface comprising a first number of data paths;
• disposing the third circuit on the substrate, the third circuit being located adjacent to the second circuit, the second memory interface being configured to couple to the first circuit;
• disposing two or more memory circuits laterally side-by-side or vertically one-on-another on the third circuit, each memory circuit comprising a second number of data paths;
• and
• coupling the second number of data paths for each memory circuit to the first number of data paths in the second memory interface to allow each memory circuit communicating with the second circuit, the first number of data paths being smaller than a sum of the second number of data paths.