Hardware Architecture of Packet Cache Eviction Engine
AssigneeGoogle Inc.
InventorsChandan Muddamsetty, Jiazhen Zheng, Weiwei Jiang, Shivang Ghetia, Abhishek Agarwal, Srinivas Vaduvatha
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Abstract
Aspects of the disclosure are directed to a packet cache eviction engine for reliable transport protocols of a network. The packet cache eviction engine can manage on-chip cache occupancy by evicting lower priority packets to off-chip memory and ensuring that higher priority packets are kept on-chip to achieve higher performance and lower latency in processing packets in the network.
Claims20
A method for evicting packets from an on-chip cache to off-chip memory, the method comprising:
- determining, by one or more processors, an occupancy counter of the on-chip cache is above a first threshold;
- selecting, by the one or more processors, a queue having a lowest priority from a plurality of queues, each queue of the plurality of queues having a configurable priority;
- removing, by the one or more processors, a packet from a head of the selected queue to evict the packet from the on-chip cache;
- and
- reducing, by the one or more processors, the occupancy counter based on a length of the packet being removed.
A system comprising:
- one or more processors;
- and
- one or more storage devices coupled to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations for evicting packets from an on-chip cache to off-chip memory, the operations comprising:
- determining an occupancy counter of the on-chip cache is above a first threshold;
- selecting a queue having a lowest priority from a plurality of queues, each queue of the plurality of queues having a configurable priority;
- removing a packet from a head of the selected queue to evict the packet from the on-chip cache;
- and
- reducing the occupancy counter based on a length of the packet being removed.
A non-transitory computer readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations for evicting packets from an on-chip cache to off-chip memory, the operations comprising:
- determining an occupancy counter of the on-chip cache is above a first threshold;
- selecting a queue having a lowest priority from a plurality of queues, each queue of the plurality of queues having a configurable priority;
- removing a packet from a head of the selected queue to evict the packet from the on-chip cache;
- and
- reducing the occupancy counter based on a length of the packet being removed.
Dependencies are inferred from the claim text.