Error rate management in non-uniform memory arrays

A method, comprising:

• sending a read address to a plurality of memory dies applying a plurality of address offsets to the read address to generate a plurality of respective offset addresses in the plurality of memory dies including at least a first offset address in a first memory die and a second offset address in a second memory die;
• reading a portion of data from a respective offset address of the memory dies including reading a first portion of data from the first offset address and reading a second portion of data from the second offset address;
• and
• decoding the portions of data of all memory dies of the plurality of memory dies including the first and second portions together.

A system, comprising:

• an Error Correction Code (ECC) circuit;
• a first array that includes a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element;
• means for applying a first address offset to read and write commands from the memory controller directed to a target address to obtain a first offset address, read data from the first offset address in the first array and send data from the first offset address in the first array to the ECC circuit for ECC decoding;
• a second array that includes a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element;
• and
• means for applying a second address offset to read and write commands from the memory controller directed to the target address to obtain a second offset address, read data from the second offset address in the second array and send data from the second offset address in the second array to the ECC circuit for ECC decoding with the data from the first offset address in the first array.