Processor restart using firmware boot from volatile memory
AssigneeMicrosoft Technology Licensing, LLC
InventorsKarunakara KOTARY, Mallik BULUSU, Michael Alan KUBACKI
Life of this patent
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Abstract
The described technology provides a method including reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors, decompressing at least a portion of the firmware code from a non-volatile memory; programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory, programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses, and communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC.
Claims20
A method, comprising:
- reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors;
- decompressing at least a portion of the firmware code from a non-volatile memory;
- programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory;
- programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses;
- and
- communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC.
One or more physically manufactured computer-readable storage media, encoding computer-executable instructions for executing on a computer system a computer process, the computer process comprising:
- reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors;
- decompressing at least a portion of the firmware code from a non-volatile memory;
- programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory;
- programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses;
- communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC,
- wherein communicating an address of the reserved portion of the volatile memory comprises setting value of a reset register on the SOC;
- and
- moving the portion of the firmware code from the reserved portion of the volatile memory on the SOC to a last level cache (LLC) of the one or more processors.
A system comprising:
- a memory;
- one or more processor units;
- and
- a processor restart system stored in the memory and executable by the one or more processor units, the service risk discovery system encoding computer-executable instructions on the memory for executing on the one or more processor units a computer process, the computer process comprising:
- reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors;
- decompressing at least a portion of the firmware code from a non-volatile memory;
- decrypting the decompressed firmware code on the reserved portion of the volatile memory;
- programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory;
- programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses;
- and
- communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC.
Dependencies are inferred from the claim text.