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US 2024/0403065 A1Published application
Parallelized boot sequence
AssigneeAdvanced Micro Devices, Inc.
InventorsSriram Sambamurthy, Indrani Paul, Kevin M. Brandl, James R. Magro, Zhao Hui Yu, Oswin E. Housty
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Abstract
The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.
Claims20
A device comprising:
- a plurality of special purpose processors configured to perform, in parallel, a power on transition sequence for the device.
A system comprising:
- a physical memory;
- at least one physical general purpose processor;
- a plurality of special purpose processors each including a local storage;
- and
- a control circuit configured to coordinate each of the plurality of special purpose processors to perform, in parallel, a power on transition sequence for the system using data stored in the local storage.
2 more elements
A method comprising:
- receiving an indication to initiate a power on transition sequence for a device;
- coordinating a plurality of special purpose processors to perform, in parallel, the power on transition sequence;
- and
- restoring a state, in parallel by each of the plurality of special purpose processors as part of the power on transition sequence, using data stored in a local storage of each of the plurality of special purpose processors.
1 more element
Dependencies are inferred from the claim text.