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US 2024/0403050 A1Published application
Vector comparison and/or population count operations
AssigneeArm Limited
InventorsJoshua Randall, Siying Feng
Life of this patent
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Abstract
The present disclosure relates generally to integrated circuits and relates more particularly to vector comparison and/or population count operations, such as for vector sorting, merging, and/or intersection.
Claims20
A circuit, comprising:
- a first register to maintain values at first ordered positions of the first register;
- a second register to maintain values at second ordered positions of the second register;
- circuitry to perform an all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register;
- and
- a matrix tile comprising an array of storage cells to store results of the all-to-all comparison.
2 more elements
A method, comprising:
- maintaining values at first ordered positions of a first register;
- maintaining values at second ordered positions of a second register;
- performing an all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register;
- and
- storing results of the all-to-all comparison in a matrix tile comprising an array of storage cells.
2 more elements
An article, comprising:
- a non-transitory computer readable medium having stored thereon instructions executable by a processing device to provide an instruction execution environment and to:
- maintain values at first ordered positions of a first register;
- maintain values at second ordered positions of a second register;
- perform an all-to-all comparison between the values maintained at the first ordered positions of the first register and the values maintained at the second ordered positions of the second register;
- and
- store results of the all-to-all comparison in a matrix tile comprising an array of storage cells.
3 more elements
A circuit, comprising:
- a matrix tile comprising an array of storage cells to store results of an all-to-all comparison between values maintained at first ordered positions of a first register and values maintained at second ordered positions of a second register;
- circuitry to accumulate comparison results for individual rows or columns of the matrix tile;
- and
- circuitry to load the accumulated comparison results for the individual rows or columns of the matrix tile into respective positions of third ordered positions of a third register.
1 more element
A method, comprising:
- storing results of an all-to-all comparison between values maintained at first ordered positions of a first register and values maintained at second ordered positions of a second register in a matrix tile comprising an array of storage cells;
- accumulating comparison results for individual rows or columns of the matrix tile;
- and
- loading the accumulated comparison results for the individual rows or columns of the matrix tile into respective positions of third ordered positions of a third register.
1 more element
Dependencies are inferred from the claim text.