Vector computation apparatus, processor, system on chip and electronic device

A processor comprising:

• a plurality of processor cores, each processor core being configured as a vector computation apparatus comprising:
• a register unit including circuitry configured to store a first vector and a second vector respectively, the register unit being divided into a plurality of computation channels, each computation channel comprising a first array comprising a first register configured to store at least one first element of the first vector and a second array comprising a second register configured to store at least one second element of the second vector;
• a thread management unit including circuitry configured to determine at least one thread according to a corresponding relationship between the at least one first element and the at least one second element;
• and
• a computation unit including circuitry comprising a plurality of execution units corresponding to the plurality of computation channels respectively, each execution unit including circuitry configured to read the first element and the second element corresponding to each thread in the corresponding computation channel according to the at least one thread, to execute a modular operation between the first element and the second element corresponding to the thread, and to write a modular operation result in the first array or second array in the computation channel.

A system on chip, comprising:

• a processor comprising a plurality of processor cores, each processor core being configured as a vector computation apparatus comprising:
• a register unit including circuitry configured to store a first vector and a second vector respectively, the register unit being divided into a plurality of computation channels, each computation channel comprising a first array comprising a first register configured to store at least one first element of the first vector and a second array comprising a second register configured to store at least one second element of the second vector;
• a thread management unit including circuitry configured to determine at least one thread according to a corresponding relationship between the at least one first element and the at least one second element;
• and
• a computation unit including circuitry comprising a plurality of execution units corresponding to the plurality of computation channels respectively, each execution unit including circuitry configured to read the first element and the second element corresponding to each thread in the corresponding computation channel according to the at least one thread, to execute a modular operation between the first element and the second element corresponding to the thread, and to write a modular operation result in the first array or second array in the computation channel.