Digital compute hardware for efficient element-wise and cross-vector maximum operations

A system comprising:

• a memory having a read port and a write port;
• an interconnection network;
• and
• a plurality of MAX compute circuits coupled to the interconnection network, each MAX compute circuit assigned a corresponding portion of each of a plurality of arriving vectors;
• wherein each MAX compute circuit is configured to:
• receive the corresponding portion of each arriving vector as a time-multiplexed set of sequences of elements,
• store each of the sequence of elements in a row of the memory,
• perform a parallel MAX( ) operation between a subsequent sequence of elements and a corresponding sequence of elements stored within the memory for a corresponding point in the time-multiplexed set,
• store a resulting sequence of elements into the memory, and
• output a final resulting sequence of elements from the memory.

A system comprising:

• an interconnection network;
• an OUT register comprising an output;
• a plurality of MAX compute circuits coupled to the interconnection network, each MAX compute circuit assigned a corresponding portion of each of one or more arriving vectors;
• wherein each MAX compute circuit is configured to:
• receive the corresponding portion of each arriving vector as a time-multiplexed set of sequences of elements,
• reset the OUT register,
• perform a parallel MAX( ) operation between a subsequent sequence of elements and an output of the OUT register and store a resulting vector in the OUT register in response to receiving the subsequent sequence of elements,
• perform MAX( ) operations across elements within the OUT register, and
• produce a scalar value representing a maximum value across the corresponding portion of all arriving vectors associated with a corresponding one of the plurality of MAX compute circuits.